Analysis of Optimization Techniques For Fully Integrated 915MHz CMOS LNA Design

This paper presents an investigation of noise figure optimization techniques for a 915 MHz CMOS Low Noise Amplifier (LNA). The research’s goal is to evaluate the trade off between fully and partially integrated solutions for 915 MHz CMOS LNA. The analysis considers an inductively source-degenerated cascode topology, which is capable of achieving simultaneous noise and input match, with narrow bandwidth and low power. Two different circuits were designed in 0.35μm CMOS technology with a supply voltage of 1.8V to evaluate the fully and partially integrated version. A noise figure of 2.97dB, gain of 11.37dB, IIP3 of 3.67dBm with 12.67mW of power dissipation were obtained through simulations for the fully integrated version, while the partially integrated one got 1.37dB, 10.11dB, -8.27dBm for the same parameters with only 2.67mW of power consumption.